US 2008/0135871 A1 discloses a reverse-conducting semiconductor device 200′ such as a reverse-conducting insulated gate bipolar transistor (RC-IGBT) as shown in FIG. 1. The device 200′ shown in FIG. 1 includes, within one wafer 100, an insulated gate bipolar transistor with a built-in freewheeling diode. As shown in FIG. 1, such a reverse-conducting semiconductor device 200′ includes an n type base layer 101 with a first main side, which is the emitter side 104 of the integrated IGBT, and a second main side, which is the collector side 103 of the IGBT and which lies opposite the emitter side 104. A fourth p type layer 4 is arranged on the emitter side 104. On the fourth layer 4, third n type layers 3 with a higher doping than the base layer 101 are arranged.
A sixth electrically insulating layer 6 is arranged on the emitter side 104 and covers the fourth layer 4 and the base layer 101 and partially covers the third layer 3. An electrically conductive fifth layer 5 is completely embedded in the sixth layer 6. Above the central part of the fourth layer 4 no third or sixth layer 3, 6 is arranged.
On this central part of the fourth layer 4, a first electrical contact 8 is arranged, which also covers the sixth layer 6. The first electrical contact 8 is in direct electrical contact to the third layer 3 and the fourth layer 4, but is electrically insulated from the fifth layer 5.
On the second main side, a seventh layer 7 formed as a buffer layer is arranged on the base layer 101. On the seventh layer 7, n type first layers 1 and p type second layers 2 are arranged alternately in a plane. The first layers 1 as well as the seventh layer 7 have a higher doping than the base layer 101.
A second electrical contact 9 is arranged on the collector side 103 and it covers the first and second layers 1, 2 and is in direct electrical contact to them.
In such a reverse-conducting semiconductor device 200′, a freewheeling diode is formed between the second electrical contact 9, part of which forms a cathode electrode in the diode, the n type first layer 1, which forms a cathode region in the diode, the base layer 101, part of which forms the diode base layer, the p type fourth layer 4, part of which forms an anode region in the diode and the first electrical contact 8, which forms an anode in the diode.
An insulated gate bipolar transistor (IGBT) is formed between the second electrical contact 9, part of which forms the collector electrode in the IGBT, the p type second layer 2, which forms a collector region in the IGBT, the base layer 101, part of which forms the IGBT base layer, the fourth layer 4, part of which forms a p-base region in the IGBT, the third layer 3, which forms a n type source region in the IGBT, and the first electrical contact 8, which forms an emitter electrode. During an on-state of the IGBT, a channel is formed between the emitter electrode, the source region and the p-base region towards the n-base layer.
The n type first layer 1 includes a plurality of fourth regions 15 with a fourth region width 16. The p type second layer 2 includes a plurality of fifth regions 25 with a fifth region width 26. The second layer 2 forms a continuous layer, in which each fourth region 15 is surrounded by the continuous second layer 2.
In FIG. 2 the first and second layer 1, 2 are shown over the whole wafer area through a cut along the line A-A from FIG. 1. This line is also indicated in FIG. 2 in order to show that the RC-IGBT 200′ does not have the same structure for the first and second layer 1, 2 over the whole plane of the wafer 100. In the upper part of the figure (see line A-A) the structure of regularly arranged fourth regions 15 and fifth regions 25 is shown. FIG. 2 shows the device beyond the line A-A of FIG. 1, which line lies in the active region 110 of the device (i.e. FIG. 2 also shows the termination area 111 of the device).
In the lower part of FIG. 2, it is shown that the second layer 2 further comprises a sixth region 27 (surrounded by a dashed line in the figure), which has a larger sixth region width 28, which is larger than the width 26 of any fifth region 25. The width 28 of a sixth region 27 plus the width 16 of a fourth region 15 is 1.5 to 5 times larger than the width 26 of a fifth region 25 plus the width 16 of a fourth region 15. The sixth region 27 is arranged at the border of the active region 110 and adjacent to or at least close to the termination region 111 of the wafer.
However, both the IGBT and diode are generating losses. The sixth region 27, which is a pure IGBT area, produces the highest losses, so that the highest temperatures occur on such areas. Due to the arrangement of the sixth region 27 on the border of the wafer, the temperature distribution in the semiconductor device is therefore inhomogeneous.
Furthermore, by the excentral arrangement of the sixth region 27 the safe operating area (SOA) of the IGBT is reduced, because the sixth region 27 extends into the junction termination area, which is an electrically non-active region. By this arrangement also snap-back effects occur more easily in the on-state mode. In the designs shown in US 2008/0135871 A1 the p doped IGBT areas are made large, but the diode areas are reduced in size by that approach, thereby making the device more sensitive for snap-back effects.